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Bit
Name
Reset
Access
Description
Enable interrupt on overflow
20.5.9 RTC_FREEZE - Freeze Register
Offset
0x020
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the RTC is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to an RTC register is updated into the Low Frequency domain as
soon as possible.
The RTC is not updated with the new written value until the freeze bit is cleared.
20.5.10 RTC_SYNCBUSY - Synchronization Busy Register
Offset
0x024
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
COMP1
0
R
RTC_COMP1 Register Busy
Set when the value written to RTC_COMP1 is being synchronized.
1
COMP0
0
R
RTC_COMP0 Register Busy
Set when the value written to RTC_COMP0 is being synchronized.
0
CTRL
0
R
RTC_CTRL Register Busy
Set when the value written to RTC_CTRL is being synchronized.
2011-04-12 - d0001_Rev1.10
286
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